VideoCardz discovered a new patent indicating that Intel has developed an L4 cache tile called Adamantine for use in some CPUs. This confirms rumors that Intel’s upcoming processor, codenamed Meteor Lake, will feature an L4 cache. The L4 cache can improve host CPU and security controller communications by providing much faster access times than DRAM.
Intel Meteor Lake L4 Cache
Adamantine is a level-4 cache, which means it sits between the CPU and main memory. This gives it several advantages over traditional caches. First, it can be much larger than a traditional cache, which means it can store more data. The L4 cache can improve performance by providing much faster access times than the main memory.
Typically, caches enhance the performance of the memory subsystem by providing the necessary data to compute cores quickly. However, Intel’s Adamantine cache may improve communication between the CPU and memory and between the CPU and the security controller. The L4 cache could be used for boot optimization and to preserve data from caches at reset to improve loading times.
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Potential Applications Beyond Meteor Lake
While the patent itself does not mention Meteor Lake, images included with it correspond to Intel’s upcoming processor. It features two high-performance Redwood Cove and eight energy-efficient Crestmont cores, a graphics chiplet based on Intel’s Gen 12.7 architecture, an SoC tile containing two more Crestmont cores, and an I/O chiplet interconnected with Intel’s Foveros 3D technology. This suggests that the Adamantine L4 cache could be used in a variety of applications, including:
- High-performance computing
- Artificial intelligence
- Machine learning
- Graphics processing
- Data center computing
Value Addition to High-End Silicon
Intel’s description of Adamantine indicates that future client SoC architectures may introduce large on-package caches that allow for novel usages. The L4 cache can improve host CPU and security controller communications by providing much faster access times than DRAM. The L4 cache could also add value for high-end silicon by offering higher pre-initialized memory at reset, potentially leading to increased revenue.
Improving BIOS Solutions for Modern Devices
Having memory available at reset could help nullify legacy BIOS assumptions and enable a faster and more efficient BIOS solution with a reduced firmware stage for modern device use cases, such as automotive infotainment systems and household robots. It also helps Automotive and robotic designs closely link SoC security with firmware phases. That in a result ensures platform security. Failing to follow recommendations reduces attack risks and protects confidential blocks, which is crucial for cars and robots.
Intel’s upcoming Meteor Lake processor is expected to feature the Adamantine L4 cache, which could improve communication between the CPU and memory and security controller, improve boot optimization, and preserve data from caches at reset. The L4 cache could also add value to high-end silicon and enable faster and more efficient BIOS solutions for modern device use cases.